Computers Are Able to Continue Their Operation Even When Problems Are Present

After reading this article you will learn about arithmetic operations performed by the computers.

1. Binary Addition :

In Binary Arithmetic 0 + 0 = 0; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 0 with a carry of 1.

This can be given in the form of a table which is called as TRUTH TABLE (refer Table 4.1).

Adding 2 Binary digits without considering the carry from the addition of the adjacent less significant digits is called Half-Addition.

G: Augend; E: Addend; S: Sum; C: Resulting Carry.

The Electronic device that performs the Half-Addition is called as Half-Adder.

The block diagram of a Half-Adder is shown in Fig. 4.2.

i. Full Addition :

In the computers, the Augend and the Addend are mostly stored in separate General Purpose Registers and the ALU performs their addition. The result will be stored in any one of the 2 registers. In small computers, each Register will be of 8 Bits and addition of two 8 bit numbers can be performed in them.

Medium size computers have 16 bit registers, Big size computers 32 bit registers and Supercomputers 64 bit Registers. When two 8 bit or 16 bit or 32 bit or 64 bit Binary numbers are added, the addition of the least significant bits will be an Half-Addition.

In the case of the subsequent digits, the carry from the previous addition has also to be added along with the two digits. This addition is called FULL-ADDITION. The Truth-Table for full addition is shown in Table 4.2.

G: Augend; E: Addend; P: Previous Carry; S: Sum; C: Resulting Carry.

The Electronic device that performs full-addition is called FULL-ADDER. The Block-Diagram of a Full-Adder is shown in Fig. 4.3.

The addition of 2 Binary Numbers with two or more digits is illustrated in the example below.

Example 4.1:

Perform the addition of the Binary numbers 1011 and 1010.

ii. Adder Circuits :

One type of Adder Circuit will contain as many Adders as the number of bits in the (size of the) General Purpose Registers. One of them will be a Half-Adder and the rest Full-Adders. The Half-Adder is to add the least significant digits and the others for adding the other digits.

Such an Adder is called a RIPPLE CARRY ADDER or PARALLEL ADDER. The block diagram of a 4 Bit Ripple Carr Adder is given in Fig. 4.4. Note that the Carry from each stage is taken to the next stage for adding and the 'Final Carry' is taken as the most significant bit in the Sum.

iii. Serial Adder Circuit:

This consists of only one Adder which will be a Full-Adder. The Augend and the Addend are each stored in a separate Register. The Binary Data in these Registers are simultaneously shifted Bit by Bit to the Right by a clock pulse. The shifted bits are added by the Full-Adder and the Sum bit is transferred to a Register. The circuit includes a CAREY FLIP-FLOP and a CYCLE COUNTER.

The carry Flip-Flop takes out the Carry from the Adder and feeds back to it so that it will be added with the bits of the next higher order from the Augend and the Addend. The Carry Flip-Flop is initialized (made to 0) initially (i.e.) while adding the least significant bits.

The Cycle Counter will be initialized at the start of the operation. After each clock-pulse (i.e.) after each addition, it will be incremented by 1. After the count in it becomes equal to the number of bits in any one of the registers, the Add Operation will be terminated.

2. Binary Subtraction :

There are 2 methods of performing subtraction of a Binary number from another Binary number, namely:

(i) Direct Subtraction, and

(ii) Subtraction by Complementary Addition.

i. Direct Subtraction :

In this: 1 – 1 = 0; 1 – 0 = 1; 0 – 0 = 0; 0 – 1 = 1 with a borrow of 1. This way of sub­tracting a Binary digit from another without considering the previous borrow, if any, is called Half Subtraction. The Truth Table for Half Subtraction is given in the Table 4.3.

M: Minuend; T: Subtrahend; D: Difference; B: Resulting Borrow.

The Electronic device that performs Half-Subtraction is called Half-Sub-tractor. The Block diagram of a Half-Sub-tractor is given in Fig. 4.6.

If the Minuend and the Subtrahend are of two or more digits, the subtraction of the least significant digit of the subtrahend from that of the minuend is half-subtraction. For the subtraction of the higher order digits the borrow resulting from the previous operation has to be taken into account. Such a subtraction is called Full-Subtraction. The Truth Table for the Full-Subtraction is given in Table 4.4.

M: Minuend; T: Subtrahend; W: Previous Borrow; D: Difference; B: Resulting Borrow. The Electronic Device that is designed to perform Full-Subtraction is called FULL-SUBTRACTOR (refer block diagram in Fig. 4.7).

The Subtraction of a Binary number of more than 2 digits from a similar number is illustrated in the Example 4.2.

Example 4.2:

Subtract 10 10 from 1111:

In the present-day computers, the method of Direct subtraction is not adopted; the method of subtraction by complementing is used instead.

The principle of subtraction by complementing can be illustrated as in Example 4.3.

Example 4.3:

Subtract (46)₁₀ from (87)₁₀ by complementing method.

Solution:

Minuend = 87.

Subtrahend = 46.

Complement of the Subtrahend = (99 — 46) = 53.

Add the minuend and the complement of the subtrahend 87 + 53 =

It is found that the result has an extra digit (ie) while the Minuend and the Subtrahend are of 2 digits, the results is of 3 digits. The extra digit (i.e.) the most significant digit in the result is called END AROUND CARRY (EAC).

This is removed and added to the least significant bit in the result itself to get the actual difference.

In the above case, the magnitude of the Subtrahend is less than that of the Minuend. Example 4.4 describes a case where the magnitude of the Subtrahend is greater than that of the Minuend.

Example 4.4:

Subtract (75) from (54) by method of complementing.

Solution :

Minuend = 54.

Subtrahend = 75.

Complement of Subtrahend = (99 — 75) = 24.

Adding minuend and complement of the subtrahend the result is 54 + 24 = 78.

There is no EAC in the result. So the actual difference will be got by complementing the result as follows and prefixing a negative sign to it.

Complement of the result (99 — 78) = 21.

Prefixing a — sign, the difference = —21.

The same procedure as the above is followed when subtraction by complementing is done with the Minuend and the Subtrahend in the Binary form except that they are stored in The SIGN- Magnitude form.

ii. Sign Magnitude Representation of Numbers :

While storing numbers in the Memory and in the General Purpose Registers, to indicate whether it is a positive or negative number, the Most Significant Bit of the number is used as the sign bit. If this bit is 1, the number is negative; else (i.e.) if it is 0, it is positive. For example, if the contents of an Eight-Bit Register is: 1 0 1 0 0 0 0 1 the number stored is -33. If it is: 0 0 1 0 0 0 0 1, the number is 33.

iii. Different Methods of Complementing :

There are 3 methods of complementing a Binary number, namely:

(i) l's Complementing;

(ii) 2's Complementing, and

(iii) Characteristic method.

The l's Complement of a Binary number is obtained by replacing the l's in it by O's and O's by l's.

Example 4.5:

Find the l's complement of 1 0 1 0 1 0 0 1.

Solution:

iv. Binary Subtraction by 1's Complementing :

The procedure for subtraction of a Binary number from another Binary number will be as follows:

(i) Store both the Minuend and the Subtrahend in the Sign-Magnitude form.

(ii) Get the l's complement of the Subtrahend, including its sign bit.

(iii) Add the l's complement of the Subtrahend with the Minuend.

(iv) Check the result to find whether there is an EAC in it. If there is, remove it and add it to the Least Significant Digit of the result, to give the actual difference.

(v) If there is no EAC, l's complement the result, to get the actual difference. Examples 4.6 and 4.7 are illustrative of the above procedures.

Example 4.6:

Show how 5 is subtracted from 7, in Binary form, by l's complementing method.

Example 4.7:

Show how 7 is subtracted from 5 in the Binary form using l's complement method.

v. Subtraction Circuit:

For complementing a Binary digit a device called INVERTOR or NOT-Gate is used (refer Fig 4.8 (a) and (b)].

The circuit for Subtraction by l's complement method will have as many Full-Adders as the number of bits in the register including the sign bit. A Full-Adder is used even for the least significant bits since EAC, if any, has to be added with them.

Investors are used one for each digit to complement the digits of the subtrahend. The complemented digits of the subtrahend are added with the corresponding bits of the Minuend by the Full-Adders (refer Fig. 4.9).

vi. Subtraction by 2's Complementing:

The 2's complement of a Binary number is obtained as follows:

(i) Write its l's complement; and

(ii) Add 1 to its Least Significant Bit. This is illustrated in the example 4.8.

Example 4.8:

Write down the 2's complement of the Binary number 1010.

Alternate Method for 2's Complementing :

There is another method of getting the 2's complement of a Binary number. The method is: "Scan the Binary number from right to left and complement all the bits appearing after the first '1' bit".

Example 4.9 illustrates this method.

Example 4.9:

Give the 2's complement of the Binary number 10 101010.

Solution:

Scanning the given number from right to left the first 1 bit that comes is next to the Least Significant Bit. Write down this 1 and the O's to the right of it as they are and complement all the bits to its left:

The result will be 01010110.

vii. Rules for Subtraction by 2's Complementing :

The steps for Subtraction of a Binary number from another Binary number by 2's comple­menting method are:

(i) 2's complement the subtrahend.

(ii) Add the 2's complement of the Subtrahend with the Minuend.

(iii) Check the Sign Bit in the result.

(iv) If it is 0, the result will directly give the difference. (The magnitude of the Minuend will b greater than that of the Subtrahend in this case)

(v) Else, if the Sign Bit is 1, 2's complement the result to get the actual difference.

Note:

The Sign Bit is not to be complemented in 2's complementing.

The above steps are illustrated in the Examples 4.10 and 4.11.

Example 4.10:

Assuming a 6 Bit configuration, inclusive of Sign Bit show how 14 is subtracted from 23 by 2's complementing method.

Example 4.11:

Assuming a 6 Bit configuration, inclusive of the Sign Bit, show how 23 is subtracted from 15, by 2's complementing method.

viii. Combined Adder Sub-Tractor Unit :

In most of the present-day computers, the same unit is used to perform Addition and Sub­traction. The subtraction will be by 2's complement method. Such a unit is called Combined Adder-Sub-tractor unit, (refer Fig. 4.10)

The circuit contains 2 AND-GATES and an OR-GATE. An And-Gate is an Electronic device that can give an output only if there are minimum 2 inputs. An Or-Gate is an Electronic device which can give an output if there is even one input only.

The Augend or the Minuend is stored in the register marked as X-Reg. The Addend or the Subtrahend is stored in the other register called as Y-Reg. If the operation is addition, an Add-Pulse is generated.

On a clock pulse, the bits in the 2 registers will be shifted one by one to the right. The bits from the X-Register will be transferred to the Full-Adder. The bits from the Y-Register will go through the And-Gate-2 and the Or-Gate to the Full-Adder. The Result will go to the Result-Register.

In case the operation is a subtraction, there will be a Subtract-Pulse, in which case the bits from Y-Register will be 2's complemented and will be transferred through the And-Gate-1 and the Or-Gate to the Full-Adder. In both cases, the result will be available in the Result Register. The Carry flip-flop will function just as in a serial Adder circuit.

ix. Subtraction by the Characteristic Method :

This method is used in the computers that use a 6 Bit sign-magnitude method of storing the Integer numbers. In this method, both the Minuend and the Subtrahend are expressed in the CHARACTERISTIC form.

The Characteristic form of a Binary Number is its Binary Expression; in excess of 32. For example, the Characteristic form of 17 is: 110001 which is 49(17 + 32). Similarly, -15 will be: 010001 which is 17(—15 + 32), in the Characteristic form.

In this method of subtraction, there is no need to find which is the subtrahend or the negative number, since both the numbers are to be expressed in the Characteristic form. It will be found that, for a positive number, the magnitude bits are the same both in the Binary and the Characteristic forms. For the negative number, the magnitude bits in the Characteristic form will be the 2's complement of the magnitude bits in the Binary form.

In this method, the steps are:

(i) Express both the Minuend and the Subtrahend in the Characteristic form,

(ii) Add both of them in their Characteristic form,

(iii) Check whether the sign bit is present in the result. If it is not present, the result itself gives the difference,

(iv) If the Sign bit is present 2's complement the result to get the actual difference.

Example 4.12 and 4.13 will illustrate these steps.

Example 4.12:

Illustrate how 15 can be subtracted from 28 in the Characteristic method.

Example 4.13:

Illustrate how 15 can be subtracted from 28 in the characteristic method.

3. Multiplication by the A LU:

The ALU uses 2 adjacent General Purpose Registers for performing Multiplication, since the result or the PRODUCT will be about double the size of either the MULTIPLICAND or the MULTIPLIER. Both the Multiplicand and the Multiplier will be in the Binary form.

The Multiplication is performed by successive Additions and shifting Right the data in the Registers by 1 bit. Besides the 2 adjacent Registers, another Register is to be used for storing the Multiplicand. Also a Counter has to be used to keep the number of Right-Shifts.

The detailed procedure will be as follows:

(i) Initialise a Counter to keep track of the number of Right-Shifts.

(ii) Load the Multiplicand in a General Purpose Register.

(iii) Choose 2 other Registers which are adjacent to each other.

(iv) Initialise the Higher Order Register (HOR).

(v) Load the Multiplier in the Lower Order Register (LOR).

(vi) Check the Least Significant Bit (LSB) of the LOR.

If it is one, add the Multiplicand to the contents of the HOR. Increment the Counter by 1. Go to step (viii)

(vii) If the LSB of LOR is zero, increment the Counter by 1.

(viii) Check the Counter. If the number in it is less than the number of bits in any one Register, go to step (vi). Else, stop.

The Product will be available in the 2 adjacent Registers.

Example 4.14 will illustrate this.

Example 4.14:

Assuming a Computer with Registers of 4 bits only, show how the multipli­cation of 13 and 9 will be executed.

Multiplication Circuit :

In Multiplication circuit also, a Serial Adder is used. (Refer Fig. 4.11 in the next page) Ro and R₁ are the adjacent registers used. Out of these, R₀ is the HOR and R₁ is the LOR. The Multiplicand is stored in the register R₂. The Multiplier is stored in R₁. A RIGHT-SHIFT signal is used to shift the bits of R₀ and R₁ by a single bit each time to the right.

If the right shifted bit from R₁ is 1 the Multiplicand and the contents in R₀ are added by the Full-Adder and the sum is each time sent to R₀. If it is 0 the addition is not performed. This is followed by the Right-shift and so on. A counter is used to keep track of the Right-Shifts and when the count in it reaches the value equal to the bits in the register, the operation is terminated and the Product is available in registers R₀ and R₁.

4. Division in Computers :

Division in computers is performed by successive Shift-Left and subtract operations. The Subtraction may be of 2's complementing method. For performing division also, 2 adjacent registers are to be used. The DIVIDEND is loaded in these 2 registers. The Divisor is stored in another register. The steps by which division is executed are given.

(i) Initialise a counter to keep track of the Left-Shifts.

(ii) Load the Divisor in a register.

(iii) Choice 2 adjacent registers and load the Dividend in them.

(iv) Shift left the contents of both the registers by 1 bit to the left.

(v) Increment the counter by 1.

(vi) Compare the contents of the HOR with the Divisor.

(vii) If the Divisor is less than or equal to the other, Subtract it from the data in the HOR. Post 1 in the LSB of the LOR. Go to step (ix).

(viii) Else, post 0 to the LSB of the LOR.

(ix) Check whether the count in the Counter is equal to the number of bits in any one register. If not, go to step (iv).

(x) If equal, stop the operation. The REMAINDER will be available in the HOR, and the QUOTIENT in the LOR.

Example 4.15 will illustrate this:

Example 4.15:

Show, how in a Digital Computer with 4 – bit registers, the division of 61 by 9 will be done.

The steps in the Division are given in the Table 4.6.

Divider Unit :

Fig. 4.12 gives the Block Diagram of a Divider Unit. The Registers R₀ and R₁ are 2 adjacent registers between which the left-shift is possible. The Dividend is moved into them from the memory. The Divisor is moved from the memory and stored in the register X.

The data in the registers R₀ and R₁ are shifted left each by one bit and the contents of R₀ are compared with the Divisor in the register X. A device called as COMPARATOR is used for this comparison (refer Fig. 4.12).

If the Divisor is less than or equal to the other, it is subtracted from R₀ at R₀ and a 1 is posted at the LSB of R₁. Otherwise a 0 is posted. The above procedure of Left-shift etc is continued until the counter which keeps track of the left-shifts equals the number of bits in any one register. Then the operation is stopped. The Remainder will now be available in R₀ and the Quotient in R₁.

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